Voltage scaling: key to embedded non-volatile memories in advanced CMOS

In this paper the voltage scaling of embedded non-volatile memories was discussed. Floating gate cells with high-K IPD and nitride trapping cells with high-K tunnel and blocking layers offer significant reduction of the program/erase efficiency. A major voltage reduction could be achieved by using phase change memory technology that is a serious contender for charge based embedded non-volatile memories in advanced sub-50 nm CMOS nodes. This paper also discusses experimental results, possibilities and challenges of memories to enable low voltage/power operation.