Design and Implementation of Decimal Reciprocal Unit

This paper presents the efficient design and implementation of a decimal reciprocal unit according to the Standard for Floating-Point Arithmetic (IEEE-754R), in which the initial approximation of the reciprocal is obtained by using a look-up table and a multiplication. An efficient look-up table creation is described in detail, and the error analysis for the ROMs of different sizes is carefully done in this paper. The presented design utilizes a 2
¹⁰
times10 bits ROM followed by three Newton-Raphson iterations. It takes 119 clock cycles to achieve the 16-digit (Decimal-64) accuracy approximation of the reciprocal of a decimal floating-point number. The proposed implementation of decimal reciprocal unit is verified with a Xilinx Virtex-II Pro P70 FPGA device and synthesized by using TMSC 0.18 mum standard cell library.