Data Stream Zero Suppression and Word Recoding Using an Accordion pipeline, an FPGA implementation

We have designed and implemented on a Xilinx SpartanIIE FPGA, a highly integrated and efficient data stream Zero Suppression machine device using an architecture based of a new type of register. A Zero Suppression machine based on flip-flops with a bypass function has been realized. The bypass flip-flop acts as a normal flip-flop but can act as a wire when the selbypass signal is active. The bypass flip-flop can connect only the registers with valid data discarding the others. A chain of this bypass flip-flops builds an accordion pipeline. The length of the pipeline depends to the number of non-zero bits in the pattern to be zero-suppressed.