Design of High-speed, Low-power FIR Filters with Fine-grained Cost Metrics

This paper outlines a new design methodology for the realization of finite impulse response (FIR) digital filter in transposed direct form. The logic complexity and logic depth of the FIR filter solutions have conventionally been evaluated based on the total number of adder units and the number of adder units along the critical paths. Such optimization criteria have short fall as adder units of different operand lengths have different complexities and they are likely to miss the real `critical paths' in physical implementation. This paper examines the holistic effects of operand length and adder structure on the area-time complexity of FIR filters. Fine-grained cost metrics based on the number of full adders and the number of full adder delays is used to compare the area and timing complexities of the multiplier blocks of FIR filters designed by different algorithms. A glitch path count estimation of the switching activities is also used to assess the relative performance on average power consumption of the FIR filters designed with different algorithms. In this paper, the authors demonstrate how these fine-grained assessments revitalize new optimization approaches to the design of high-speed and low-power FIR filters