VLSI Architecture for Variable Block Size Motion Estimation in H.264/AVC with Low Cost Memory Organization

A 1D full search variable block sizes motion estimation (VBSME) architecture is presented in this paper. By properly choosing the partial sum of absolute differences (SAD) registers and scheduling the add operations, the architecture can be implemented with simple control logic and regular workflow. Moreover, only one single-port SRAM is required to store the search area and then reduces 72.7% hardware cost of SRAM. The design is realized with TSMC 0.18mum 1P6M technology with a hardware cost of 67.6K gates. In typical working condition (1.8V, 25degC), a clock frequency of 266MHz can be achieved