A half-micron ferroelectric memory cell technology with stacked capacitor structure

A half-micron ferroelectric technology applicable to mega-bit non-volatile memories is reported. 10.5 /spl mu/m/sup 2/ 1transistor/1capacitor cell with a stacked capacitor structure is successfully achieved using planarization by CMP (chemical mechanical polishing), dry etching at the high temperature and TiO/sub 2/ diffusion barrier technologies. The capacitance above 50 fF is obtained at the size of 1.5 /spl mu/m/spl times/1.5 /spl mu/m, which satisfies the primary requirements for 4M NVDRAM operation.<
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