A highly manufacturable trench isolation process for deep submicron DRAMs

A simple Shallow Trench Isolation (STI) process is proposed for deep sub-micron DRAM applications. The features of this STI flow are tapered trench sidewalls, a slight trench reoxidation, a vertical B field implant, a CMP-only planarization, and disposable oxide spacers to smooth the trench corners. The scalability of this process makes it suitable for 256 Mb to 4 Gb DRAM generations.<
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