A drive-level error rate model for component design and system evaluation

A drive-level model for gated peak detection channels in the presence of off-track interference is presented. Input to the model can be digitized readback patterns from testers, disk drives, or recording process simulations. The model predicts bit error rate as a function of amplitude qualification threshold in the form of a threshold error rate (TER) plot. Data patterns are described which increase the likelihood of the three types of errors in gated peak detection disk drives: drop-ins, drop-outs and shifted bits. The importance of designing for drive-level performance, rather than component-level performance is discussed. Examples of using the model to determine design targets for head, media and channel parameters are given for inductive and magnetoresistive applications. The optimum design targets for some key parameters are found to change in the presence of off-track interference.<
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