Impact of LDD spacer reduction on MOSFET performance for sub- mu m gate/space pitches

The impact of very thin sidewall LDD spacers which are required to allow sub- mu m gate/space pitches on MOSFETs is discussed for the first time. The effects of LDD spacer materials, LPCVD TEOS and nitride, on the device characteristics and short channel behavior of n and p-channel MOSFETs are analyzed. We show that the main issue related to sub-100 nm spacers is gate-induced drain leakage and not device reliability. Nitride spacers improve device reliability and current drive but result in higher levels of gate-induced drain leakage. Our findings show that for sub-half mu m devices, spacer thickness reduction down to 600 AA has no appreciable effect on lifetime.<
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