Novel read disturb failure mechanism induced by FLASH cycling

The read disturb failure mechanism reported causes unselected erased bits residing on selected wordlines to gain charge under low field conditions, causing them to appear programmed. This failure appears to be due to electron tunneling barrier lowering by positive charge trapped during program/erase cycling. The Si-SiO/sub 2/ barrier in failing bits is reduced from 3.0 eV to under 1.0 eV at 70 degrees C. The FLASH EPROM array failure rate dependence on cycling, stress voltage, temperature, and duty cycle is characterized. A low failure rate has been found for the fabrication process studied.<
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