A superfast algorithm for single-error correction in RRNS and hardware implementation

A superfast algorithm for correcting single residue errors in the RRNS (redundant residue number system) is developed with a slight increase in redundancy. Based on this algorithm and another recently proposed fast algorithm, two architectures are designed for their hardware implementation. The hardware complexity for this superfast algorithm is O(k) while the hardware complexity for previously known algorithm is O(k/sup 2/).<
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