A high-resolution multibit Sigma Delta ADC with digital correction and relaxed amplifier requirements

A second-order multibit Sigma Delta (sigma-delta) analog-to-digital converter (ADC) with a 4-b internal quantizer is described. It uses a simple and fast digital correction scheme. A correlated-double-sampling (CDS) fully differential integrator was used, in which the op amp needed only a low slew rate and moderate bandwidth for a sampling rate of 5.25 MHz. A second-order modulator was fabricated in the standard MOSIS p-well 2- mu m CMOS process. The excellent measured linearity and high S/(N+D) ratio (95 dB with an oversampling ratio of only 128) of the corrected converter verified the practical advantages of the proposed architecture.<
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