Gate Leakage Properties of MOS Devices with Tri-Layer High-k Gate Dielectric

Gate leakage of deep-submicron MOSFET with stack high-k dielectrics as gate insulator is studied by building a model of tunneling current. Validity of the model is checked for MOSFET's with SiO2 and high-k dielectric material as gate dielectric respectively, and simulated results exhibit good agreement with experimental data. The model is successfully used for a tri-layer gate-dielectric structure of HfON/HfO
2
/HfSiON with a U-shape nitrogen profile and a Si/SiO
2
-like interface, which is proposed to solve the problems of boron diffusion into channel region and high interface-state density between Si and high-k dielectric. By using the model, the optimum structural parameters of the tri-layer dielectric can be determined. For example, for an equivalent oxide thickness of 2.0 nm, the tri-layer gate-dielectric MOS capacitor with 0.3-nm HfON, 0.5-nm H
f
O2 and 1.2-nm HfSiON exhibits the lowest gate leakage.