A VLSI architecture for motion compensation interpolation in H.264/AVC

A VLSI architecture for motion estimation/compensation interpolation in H.264/AVC is presented in this paper. Compared with previous work, this architecture has following characteristics: First, it supports all block modes and fractional samples adopted in H.264/AVC standard. Second, no extra initiation and finalization time is required, which enhances the system performance. Third, a pipelined finite impulse filter (FIR) is used to replace the traditional adder tree, which increases the system clock frequency. Because this design applies full pipelined architecture, it can generate one half sample in every cycle and eight quarter samples in every nine cycles with little pipeline latency. In fact, this architecture with minor revision could be adopted in MPEG-4 and other video coding standards. The design is implemented with TSMC 0.18/spl mu/m CMOS technology. The core area is 0.577/spl times/0.661mm/sup 2/ and frequency is 274MHz in typical condition (1.8V, 25/spl deg/C).