Data retention of silicon nanocrystal storage nodes programmed with short voltage pulses

In this paper, data retention of nonvolatile memories with silicon nanocrystal discrete storage nodes is theoretically and experimentally investigated. Samples under test were memory arrays of 256/spl times/10/sup 3/ cells with 4-nm-thick tunnel oxide. Charge loss of cycled arrays was monitored using the gate-stress (GS) technique. A first set of samples was cycled by applying the conventional program and erase pulses on a millisecond timescale. Experiments showed different features as a function of the GS time, namely: 1) a fast discharge at short times and 2) a much slower leakage mechanism at long times. Leakage was analytically modeled by taking into account trap-assisted tunnel and direct tunnel at short and long times, respectively. Afterward, starting from the dynamics ruling the mechanism of creation of a new trap, another set of samples was cycled with pulsed voltage waveforms of suitable duty cycle and pulses on a microsecond timescale. In this case, the fast discharge was inhibited, and data retention consistently improved. The latter behavior was modeled in terms of a much lower trap density compared to that in the conventional cycling. The advantages of pulsed tunnel programming technique over the standard one in terms of data retention are definitely assessed.