Study of on-chip integrated antennas using standard silicon technology for short distance communications

A study of on-chip integrated antennas has been carried out in order to test the feasibility of antenna implementation on silicon circuits using standard microelectronics technologies. On-chip integration of a 10-20 GHz dipole antennas coupled to VCOs using standard BiCMOS7/spl trade/ (0.25/spl mu/m) STm process has been investigated. The antenna configuration (10 GHz circuit) is a folded dipole: 2.7 /spl times/ 4.48 mm/sup 2/. For a RF power injected from VCO to the antenna of -7dBm, the EIRP is about -15dBm, the maximum gain about -8 dBi. The radiation efficiency can be estimated at 10%. Considering the antenna-VCO circuits working at 20 GHz, much higher values of radiation efficiency (30%) and gain (-5 dBi) were measured. These promising results tend to demonstrate that on-chip integration of antennas with the RF front-end circuits should be possible in the case of miniaturized communicating objects dedicated to short range applications above 10-20 GHz.