A Synchronization Coprocessor Architecture for WCDMA/OFDM Mobile Terminal Implementations

Wireless communications are evolving towards multistandard systems. The complexity of mobile terminals will increase dramatically as multiple radio interfaces need to be supported. Programmability will be essential in order to manage the increased complexity of the receiver baseband processing, and to minimize product development time. A programmable coprocessor architecture is presented that is targeted for implementing the synchronization algorithms of WCDMA and OFDM receivers. The coprocessor is a part of a programmable WCDMA/OFDM baseband receiver platform targeted for dual- mode mobile terminal implementations. The coprocessor architecture is presented and the programming interface designed for the coprocessor is explained in detail. The coprocessor has been implemented with a register-transfer-level VHDL description and synthesis with 0.13 mum standard cell CMOS technology. Simulation and synthesis results are given.