Effects of data rate and transistor size on single event upset cross-sections for InP-based circuits

We present results from SEU testing of two limiter-amplifier ASICs. The circuits are electrically identical except that they are fabricated using different generations InP-based HBT technology. Cross sections measured at clock speeds of 6.4 and 12.8 GHz show technology dependence, and are analyzed to determine charge collection dynamics. Our results agree with previous simulations, as well as experiments on similar technologies