The next generation integrated MEMS and CMOS process on SOI wafers for overdamped accelerometers

We developed a MEMS process for the manufacture of accelerometers that combines CMOS processing on SOI wafers. Unit processes for electrical isolation trench fabrication, MEMS structural release, and CMOS foundry compatibility were developed for robustness and reliability. Current-voltage measurements of the isolation trenches show that the trench leakage is < 0.4 nA even at 100V; leakage at the operational voltage of 5V is < 1.63 pA. A "pedestal and bridge" photolithography process was developed to etch away the underlying sacrificial buried oxide to release the MEMS structures. These processes were developed and adapted to ensure the best compatibility with a given 0.6 /spl mu/m foundry CMOS process for volume production of a particular accelerometer designed for overdamped applications, such as vehicle crash sensing.