Thermionic emission probability for semiconductor-insulator interfaces

Simulation of hot-carrier gate-current effects in either MOSFET or MODFET devices requires knowledge of the carrier-emission probability over the semiconductor-insulator barrier. Several works in the recent past have relied on a limiting form for this probability that can lead to significant errors for large fields in the Si-SiO
2
system. This brief shows that the result for emission probability can be expressed as an error function, leading to simple implementation in the numerical 2-D simulators commonly used in device analysis. The result is compared to the commonly used limiting form for both large and small values of the normalized barrier height.