High speed CMOS technology for ASIC application

In order to realize high speed and high density CMOS logic LSI's, an advanced two-level metal CMOS technology, having minimum feature size of 1.0 µm, has been developed. The technology has proven very high speed feasibility of CMOS logic arrays of less than half-nsec delay times, in addition to high reliability of 5V operation. BCD
³
structure is employed for 1.0 µm N-channel MOS transistor, which realizes both high current gain and very high reliability for hot-electron degradation. Al/MoSix/Ti contact system and interlevel dielectric planarization process have been newly developed for high performance interconnections. To experimentally verify the effectiveness of the technology with 1.0 µm design rule, a 7K gate-array has been fabricated and its electrical characteristics has been examined.