Modeling and VLSI design constraints of substrate current

Some VLSI design constraints due to substrate current will be discussed and a simple closed form expression for short channel MOS transistor substrate current is proposed. This model is based on the physical operating principle of impact ionization, as well as the electric field dependence on drain and gate voltage. By using this model, the calculated substrate current of a transistor with L
eff
≃ 1.5 µm was found to be within 10% of measured values over the operating range of interest. In addition, this model also correctly predicts parasitic bipolar breakdown phenomenon as a function of gate voltage. Because of its simplicity, the model has been easily implemented into a computer-aided circuit analysis program to simulate the actual circuit with very little increase in execution time.