Nanowatt devices

Present emphasis in device research is placed on higher speed and higher power output. This is partly a consequence of the fact that the majority of present information-handling schemes are based on serial processes, and data processing capacity is proportional to the speed of the individual devices. On the other hand there is a large area of present and potential problems where information would better be processed in parallel channels or in arbitrary combinations of parallel and serial paths. The latter approach to data handling calls for systems with a very large number of devices, most of them active or at least switchable. This number may be in the high millions. Under these circumstances power consumption and size become of greatest importance. This paper therefore investigates the question of the lower limit for the power consumption of active solid-state devices, or, in other words: Utilizing known physical principles, for how low a power consumption can one design and fabricate active devices? As an introduction the paper briefly describes the design, fabrication and performance of integrated amplifier and digital function blocks operating at supply power levels of 1 to 10 microwatts. Then the paper analyzes the problems encountered if the supply power is lowered into the range between 1 nanowatt and 1 microwatt. These are (a) basic physical limitations, (b) noise, (c) speed, and (d) technological limitations (pointing to potentially profitable areas of research). The results of experiments with some exploratory devices are described and the conclusion is drawn that the next few years will see the 1 to 1000 nanowatt supply power range opened up for practical device applications.