Practical high-resolution programmable Josephson Voltage standards using double- and triple-stacked MoSi/sub 2/-barrier junctions

We have developed vertically stacked superconductor normal-metal-superconductor Josephson junction technology for the next-generation quantum voltage standards. Stacked junctions provide a practical way of increasing the output voltage and operating margins. In this paper, we present fully functioning programmable voltage standard chips with double- and triple- stacked MoSi/sub 2/ barrier Josephson junctions with over 100 000 junctions operating simultaneously on a 1 cm /spl times/ 1 cm chip. The maximum output voltages of the double- and triple-stacked chips were 2.6 V and 3.9 V, with respective operating current margins of 2 mA and 1 mA. A new trinary-logic design is used to achieve higher voltage resolution. Thermal transport in these high-density chips will be briefly discussed.