A new method for extracting base resistance in bipolar transistors

The base resistance extraction method presented by Linder and coworkers (2001) requires an array of dual-base npn test structures to separate the intrinsic base resistance from its extrinsic counterpart (denoted as R/sub BI/ and R/sub BX/, respectively). This requirement imposes real-estate constraints, especially when the nonproduct silicon area is limited. In contrast, we propose a new technique for R/sub BI/ and R/sub BX/ extraction using only one (rather than multiple) dual-base devices. The physics behind this technique is that current injection swings from one side of the emitter window to the other as a result of a polarity switch of the dc bias difference (/spl Delta/V/sub B/) between the two separate bases. Specifically, as a constant current I/sub E/ is pulled out of the emitter, the emitter voltage (V/sub E/) is monitored as a function of /spl Delta/V/sub B/. A closed-form solution for the partial derivative of V/sub E/ with respect to /spl Delta/V/sub B/ is derived from a physics-based model. The solution predicts that k/sub 1/+k/sub 2/=1 and R/sub BI//R/sub BX/=k/sub 1//k/sub 2/-1, where k/sub 1/ and k/sub 2/ are defined as the asymptotic values of the V/sub E/ versus /spl Delta/V/sub B/ slopes at very high positive and negative /spl Delta/V/sub B/, respectively. A dual-base test structure with an emitter size of 0.4/spl times/4.0 /spl mu/m/sup 2/ is fabricated using a self-aligned, double-poly process, and k/sub 1/=0.85 and k/sub 2/=0.15 are extracted. As a result, we obtain R/sub BI//R/sub BX/=4.67 and an intrinic base sheet resistance of 15.7 k/spl Omega///spl square/.