A 2.5-V 14-bit /spl Sigma//spl Delta/ CMOS SOI capacitive accelerometer

This paper presents a 2.5-V 14-bit fully differential /spl Sigma//spl Delta/ interface circuit in 0.25-/spl mu/m CMOS technology for a high-resolution silicon-on-insulator capacitive accelerometer fabricated using a simple CMOS-compatible stictionless process. The integrated circuit is based on programmable front-end back-end first-order /spl Sigma//spl Delta/ architecture and provides a 1-bit pulse-width modulated digital output. Using correlated double sampling, the low-frequency noise is suppressed by 10 dB. Capacitive resolution is 22 aF at 75 Hz (resolution bandwidth = 1 Hz), equivalent to 110 /spl mu/g with a dynamic range of 85 dB (14-bit resolution) and a sensitivity of 500 mV/g. The chip occupies 2 mm/sup 2/ and consumes 6 mW.