Design of fast Josephson arithmetic circuits

A Josephson 2-b full adder and a 4-b parallel multiplier are designed using an advanced design with speed optimization of functional direct coupled logic. Wide margins EXOR, majority 2/3, and delay gates implemented with picosecond junctions (R/sub C/C=2 ps) are presented and their performances are analyzed. The adder consists of 10 gates with 90 Josephson junctions and dissipates 30 mu W. The propagation time along the critical path is 10 ps/b near threshold bias. It rises only at 20 ps/b in the adder at 80% of the maximum bias. The multiplier consists of 60 gates and dissipates 180 mu W. The propagation times along the critical path near threshold bias, and at 80% of maximum bias are respectively 60 ps/b and 100 ps/b.