Optimizing the output impedance of a power delivery network for microprocessor systems

This paper presents a systematic design oriented frequency domain analysis of a multi-stage power distribution network. (PDN) of a microprocessor system with the power source represented as,a close-loop small-signal model of a dc to dc, converter. Generalized analytical expressions are derived for the output impedance including voltage sensing at different, stages. of, the multistage PDN. The affect of optimally selecting the ESR, ESL and capacitance of the decoupling capacitors at different stages of the PDN is described in terms of the converter's loop gain, crossover frequency, phase margin and their impact on realizing the flat output impedance at the microprocessor core. Simulation results are presented to support the validity of the novel design oriented analysis.