Modeling and simulation of time domain faults in digital systems

The purpose of this paper is to present and discuss a novel modeling and fault simulation technique for two types of dynamic faults in digital systems: transient power supply voltage drops and transient delays in logic elements or signals paths. Techniques and tools currently used for permanent faults are reused for dynamic (permanent) and intermittent faults. For transient power supply voltage drops (/spl Delta/V/sub DD/), two approaches are proposed: delay fault injection in all logic elements of the CUT (circuit under test), or modulation of the clock and observation rate. For transient delays (e.g., SEU), single delay injection is performed at logic element level. Delay modulation is carried out by fault injection using the PLI interface of the commercial Verilog/spl trade/ simulation tool. Preliminary results, demonstrated by the c7552 ISCAS'85 benchmark circuit, show that CUTs with long critical paths are very sensitive to power supply transients. Moreover, a pseudo-random test pattern can be used to identify the dependence of the CUT sensitivity to delay faults on defect size, for a given clock period, /spl tau//sub o/.