Architectural and implementation challenges in designing high-performance RSFQ processors: a FLUX-1 microprocessor and beyond

This paper discusses the major challenges and solutions in designing high-performance superconductor processors in the context of the on-going collaboration between SUNY Stony Brook, TRW, and the JPL (NASA). It presents the architecture and organization of the first 8-bit FLUX-1 RSFQ microprocessor with a target clock frequency of 20 GHz fabricated in TRW's 4 kA/cm/sup 2/, 1.75-/spl mu/m Josephson junction technology in 2001-2002. A new parallel partitioned architecture has been developed for FLUX-1 in order to fill its long processing pipelines with operations, and reduce interconnect delays. The latest version of FLUX-1, called FLUX-1R, with improved circuit design characteristics and decreased power dissipation was fabricated in July 2002. FLUX-1R contains 63,107 Josephson junctions on a 10.35 mm /spl times/10.65 mm die with flip-chip packaging. The chip is currently under testing at TRW.