Negative-resistance MOS transistor

The author proposes a novel approach for implementing a negative-resistance MOSFET that uses a non-uniform drain-current flow within one integrated structure. This MOS device exhibits a negative output conductance within a specific bias range as a consequence of current sharing between two MOSFETs of different geometries. The author describes a negative-resistance MOS transistor and discusses in detail its principle of operation, design, and electrical characteristics. The MOSFET is a three-terminal voltage-controlled device that consists of two MOS transistors with the same type of channel conductivities and can be implemented either in n-channel or p-channel versions. The proposed device is a compact element that can be fabricated together with other semiconductor devices using a standard CMOS technology.<
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