Power reduction via an MTCMOS implementation of MOS current mode logic

In this paper, MOS current mode logic (MCML) is implemented in a multi-threshold CMOS technology. The design scheme allows the reduction of the minimum operational supply voltage, as well as the elimination of level shifters used. A high-speed 1:8 2.5 Gbit/s demultiplexer is used as a test vehicle. A 37% power saving is achieved. Furthermore, the impact of using the MTCMOS implementation over circuit parameters such as output impedance, current-matching-ratio, common-mode-rejection-ratio, gain, threshold voltage fluctuations and frequency response is investigated. This work is important for industry since the MTCMOS technique opens a new alley for reducing power in MCML high-speed implementations while attaining the required data rates.