High speed current mode logic for LSI

A high speed/low power logic family is described which combines the best features of current mode logic (CML), emitter-coupled logic (ECL), and emitter function logic (EFL). This is combined with a low voltage-current source, using the principle of current imaging, to provide three levels of series gating with reduced supply voltages. With relatively slow transistors (
f_1
=500 MHz) circuit structures have been fabricated which provide several logic levels with a total delay of 2
ns
and total power dissipation of 2 mW per circuit structure. The paper also describes the implementation of ROM's, RAM's, and PLA's using the principle of current steering. An analysis is given for circuit operation with variation in supply voltage and temperature. Three fabricated LSI chips are described with an average of 1000 equivalent gates per chip.