Effect of high k dielectric layer on the performance of Silicon based Nanoscale MOSFET

In this paper, the effect of High K dielectric layer on Silicon based Metal-oxide-semiconductor field-effect transistors (MOSFETs) was studied. As we know MOSFET place a very important role in modern electronics, this work investigates the relationship between drain current and gate voltage in MOSFETs with different High K dielectric materials. The dielectric layer in MOSFETs separates the gate electrode from the semiconductor channel, controlling the flow of current through the device. Silicon dioxide (SiO2) has historically been the dielectric of choice due to its excellent insulating properties and compatibility with silicon technology. However, as transistor dimensions shrink and performance demands increase, alternative dielectrics with higher permittivity (high-k dielectrics) have gained more prominence. Consequently, MOSFETs employing high-k dielectrics exhibit enhanced performance characteristics, including lower threshold voltages and higher drain currents at equivalent gate voltages compared to SiO2 based MOSFETs. To understand the dielectric properties of different High-k materials, gate voltage, and drain current is essential for optimizing the MOSFET performance. In this work Al2O3, HfSiO4, and HfO2 which has high dielectric constant than SiO2 were used to study the MOSFET performance. The HfO2 dielectric layer shows more current then the remaining dielectric layers.

I. Introduction

The advanced semiconductor based electronic devices are scale down to sub nanometer level, the size of the device is further getting reduce as per Moore’s law[1]. The ITRS, or International Technology Roadmap for Semiconductors, plays a vital role in driving innovation and advancements in the semiconductor industry[2]. One of the primary areas of attention for the ITRS is the miniaturization of active components in electronic devices[3],[4]. This push towards smaller and more efficient components has led to the transition from traditional bulk CMOS FETs to nanoscale ultrathin body Silicon on Insulator(SOI) structures[5],[6]. The use of ultrathin body SOI structures offers several advantages over bulk CMOS FETs[6]. One of the main benefits is the improved subthreshold slopes, which results in better overall device performance. Additionally, the reduced short-channel effects help to enhance the reliability and longevity of the electronic devices. The enhanced electrostatic control achieved by thinning the silicon body above the buried oxide layer is a key factor in the improved performance of ultrathin body SOI structures. This allows for more precise control over the flow of electrons within the device, leading to better overall efficiency[7],[8]. To further improve the performance of these devices, high-K dielectrics such as HfO₂ or ZrO₂ are used to mitigate gate leakage currents. These high-K dielectrics help to decrease tunneling leakage while still maintaining the necessary gate capacitance for optimal device operation[7]. When paired with a thin SiO2 layer to create a gate stack, these materials help to ensure that the device operates at peak efficiency. It was investigated how high-k dielectric materials affected the electrical performance of Gate-all-around and Double Gate MOSFETs[9]. High-k dielectrics offer higher gate capacitance, allowing for improved electrostatic control of the channel and reduced gate leakage current along with this the choice of dielectric influences the interface quality between the dielectric layer and the semiconductor, affecting carrier mobility and scattering mechanisms within the channel region[11]-[14].