: A Memory-Efficient Tri-Stage Polynomial Multiplication Accelerator Using 2D Coupled-BFUs

Polynomial multiplication (PM) is the computational bottleneck of lattice-based cryptography, such as post-quantum cryptography (PQC). Designing dedicated hardware accelerators for polynomial multiplication is an effective solution to improve the execution speed. However, current mainstream designs ignore the impact of computing array size, resulting in poor design flexibility and low memory utilization. To address these issues, we propose, a memory-efficient tri-stage PM accelerator. Our proposed tri-stage PM algorithm fuses all isolated substages into a unique stage named fused coefficient-wise multiplication (FCWM), ensuring efficient computation. Meanwhile, in different stages of the algorithm, the circuit of two-dimensional reconfigurable coupled butterfly units (2D-RCBFUs) is fine-grained reconfigured to improve resource utilization. Moreover, the low-complexity memory mapping scheme simplifies the address control logic and reduces the hardware overhead. can efficiently support the PM of an arbitrary power of two, which is impossible for previous designs using a 2D computing array. Compared with the state-of-the-art designs, our demonstrates the best memory utilization, achieving up to
$10.0\times$
performance improvement.