Multi-Stage Jitter-Reduction and Frequency Multiplication for 54 GHz ATE Clocks

This paper introduces a 4-stage jitter reduction circuit with 2 stages of frequency doubling to produce an ultra-low jitter, 54 GHz clock, synchronized to a 13.5 GHz ATE/BERT/FPGA reference signal. Jitter-reduction is achieved using 4 stages of real-time signal averaging, each with nominal reduction of 30%. The effects are cascaded to obtain ~3 times reduction in random jitter (RJ). The clock frequency is doubled twice to obtain a desired output frequency of 54 GHz, suitable for testing 54 Gigabaud and 108 Gigabaud devices (using double data rate, DDR clocking). Experimental results demonstrate reduction of random jitter below 200 femtoseconds.