Timing-violation-soft PUF design based on carry-lookahead adder

With the development of Internet of Things technology, there is an increasing demand for security protection under extreme resource-constrained conditions. Hardware-based physical unclonable functions (PUFs) become less effective as they require hardware replacement. In this paper, a design scheme of timing-violation-soft PUF (TVS PUF) based on carry-lookahead adder (CLA) is proposed for resource-constrained systems, by studying the metastable characteristics of flip-flop under timing violation status and the transmission path delay deviation of arithmetic operation circuits. Firstly, a synchronous timing module (STM) composed of a 32-bit CLA and flip-flops is constructed using Xilinx Artix-7 FPGA. Then, timing violation are induced in the STM by increasing the clock frequency using a Mixed-Mode Clock Manager (MMCM). Finally, by comparing the output values of the STM under timing violation status with those under normal operation status, the parity of flipped bits is used as the judgment criterion for PUF response, establishing the mapping relationship between challenges and responses. Experimental results demonstrate that the proposed PUF can utilize the existing hardware structure to generate 2
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challenge-response pairs (CRPs), exhibiting good randomness (passing 12 NIST test items), uniqueness (49.93%), and reliability (97.39%). When collecting up to 10
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groups of CRPs, the attack prediction rates of four common machine learning algorithms remain close to the 50% baseline of random guessing.