Hardware Design of Linear Active Disturbance Rejection Control Based on Floating-Point Operations

Linear Active Disturbance Rejection Control (LADRC) has been widely employed in automatic control due to its enhanced robustness and superior anti-interference capability. However, most current LADRC applications are based on the software level, which exhibits a relatively low response speed compared to the hardware implementation and does not apply to specific scenarios requiring high response speed. This paper presents a hardware design of LADRC based on a single-precision floating point, which guarantees arithmetic precision and a high response speed. The feasibility of this hardware implementation is demonstrated by applying it in a fully integrated digitally controlled BOOST circuit under a 180 nm process. The proposed LADRC in this paper shows a 20% improvement in response speed in BOOST circuits while maintaining stability ripple at 0.9% of the target output with a maximum error of 0.6%.