High Speed Single Precision 64-Tap FIR Filter Using Urdhva Tiryagbhyam Sutra

In high computing applications like signal and image processing, the computational demand for floating-point multiplication remains paramount. However, the intrinsic complexity of this operation translates into substantial time and power consumption. Addressing this challenge, this paper presents a novel and efficient methodology for IEEE 754 floating-point 64-tap FIR Filter, with a primary emphasis on minimizing both delays in time and area utilization. The Urdhva Tiryagbhyam sutra is used to reduce the delay in multiplication. This paper presents a process to devise filter coefficients and implementation of them for 64-tap 32-bit FIR filter design, which are modeled in Verilog HDL and implemented for XC7K70TFBV676-1 Kintex-7 FPGA board in Xilinx Vivado Tool. The obtained results prove that the proposed FIR filter design proves to be better than the existing FIR filter design as it reduces area by 51.11%, delay by 45.83% and power dissipation by 19.49%. Also the proposed FIR filter design proves to be better than the existing FIR filter design as it reduces Area Delay Product by 73.52% and Power Delay Product by 56.39%.