VLSI Implementation of Modified Karatsuba Multiplier for Low Power Applications

In electronic gadgets era, multi-digit multiplication has found extensive applications in many fields such as numerical computation, complex arithmetic and primitive testing process. There is a rising demand for systems that offer high performance which requires minimal energy, particularly in domains like image processing and cryptography, where complicated techniques are employed. This paper aims to design and explore the hardware architecture for multi-digit multiplication and evaluates its VLSI implementation, taking into account both cost and performance considerations. The design of modified architecture of Karatsuba multiplier is proposed specifically for low power application. The final vector merging addition is performed using sum based carry calculation to reduce a computation delay. The findings will aid system designers to choose design alternatives, including ASIC implementation, for applications that necessitate multi-digit multiplication.