Optimized Trench IGBT With Dummy Gate and Buried n-Type CS Layer for Substantial Reduction of Power Loss and EMI Noise

A novel optimized trench insulated-gate bipolar transistor (TIGBT) with dummy gate and buried n-type carrier stored layer (DGBN-TIGBT) is proposed and investigated in this article. The heavily doped buried n-layer embedded in the p-body region of the proposed device not only enhances the conductivity modulation in the drift region without producing a negative impact on the breakdown voltage (BV) but also forms a self-adaptive hole path through the integrated pMOS with the dummy gate (DG). Moreover, the lower p-type region is connected to the emitter via the pMOS adaptively during the switching transient, which reduces the gate-collector capacitance (
${C} _{\text {GC}}$
) and mitigates the accumulation of holes near the corner and bottom of the gate trench. This enables lower power loss and suppressed electromagnetic interference (EMI) noise. Simulation results show that compared with the conventional carrier stored trench bipolar transistor (CSTBT), the ON-state voltage drop (
${V} _{\text {CE}{\text {ON}}}$
) at a current density of 200 A/cm2 is reduced by 24.2% and
${C} _{\text {GC}}$
at
${V} _{\text {CE}}$
of 25 V is reduced by 42.6%, respectively. The turn-off loss (
${E} _{\text {off}}$
) is also reduced by 60.9% with the same
${V} _{\text {CE}{\text {ON}}}$
of 0.97 V. Furthermore, the reverse recovery dVAK/dt of the freewheeling diode (FWD) is dropped by 23.6% with the same turn-on loss (
${E} _{\text {on}}$
) of 14 mJ/cm2. Therefore, the common-mode (CM) noise can be reduced up to
$12.9~\text {dB}\cdot \mu $
V for the proposed device in the frequency range of 40–100 MHz.