Approximate Vedic Multiplier Architecture for Efficient CNN Acceleration on Embedded Devices

Advancements in deep neural network accelerator architectures have resulted in the proliferation of Convolutional Neural Network (CNN) applications in computer vision. These energy-efficient accelerators provide considerable performance improvement and incur low area overhead. Due to restricted power and area constraints, this enables the accelerators to be ideally suited for several real-time mobile and edge device applications However, the major challenge is deploying the continuously growing, complex deep CNN s on embedded devices that are constrained in nature in terms of area and power. In addition, these applications generate an enormous amount of data, and accommodating them in an embedded device is also challenging. To alleviate the computational complexity of CNNs on embedded devices, this work proposed an algorithm that introduces a design trade-off between accurate computation and approximate computation. The approximate computing method reduces the computation workload and enhances the speed as well as the power efficiency of error-resilient applications. We present an approximate Vedic multiplier architecture optimized for area, power, and delay. An accelerator architecture has also been developed that computes the CNN inference model in multiple channels parallelly without any penalty on the network's accuracy or the hardware cost. It is shown in the experimental analysis that the proposed computing architecture enables the embedded devices to work with low power and area. The proposed accelerator achieves a 5.3 % improvement in computing throughput over the state-of-the-art accelerators.