An End-to-End Agile Design Framework to Improve Energy Efficiency on CGRAs

In this paper, we propose a domain-specific frame-work that integrates Chisel-based Coarse-grained reconfigurable architecture (CGRA) Modeling, RTL generation, Architecture Graph Intermediate Representation (IR), dataflow graph (DFG) Mapping, interconnect exploration, and physical implementation. Within this framework, we propose an interconnect exploration flow based on a novel interconnect architecture called Matrix, which realizes a heterogeneous interconnect architecture for a set of specific applications by application mapping, design space exploration (DSE) and pruning. We design an agile mapper built on a graph-based two-level architectural IR, which better adapts to the flexible interconnect model and enables greater interconnect exploration to improve the mapping success rate. Experiments show a significant reduction in architecture area, improved energy efficiency, and high PE utilization compared to the state-of-the-art tool, with high-quality mapping results due to architecture tuning. Additionally, our pruning strategies reduce interconnect paths in the Matrix, ensuring interconnect efficiency and further improving PE utilization.