IoT Gateway Bulk Driven Quasi Floating PLL Logic In 5G Wireless Communication

Modern radio communication equipment makes significant use of Phase Locked Loop (PLL) frequency synthesizers. Users can choose from a set of frequencies to generate a set of frequencies based on one reference. We use conventional PLLs using complementary metal oxide semiconductors (CMOS) and BD MOS transistors configured in a pass transistor mode to design a PLL that reaches 140 MHz. Circuits have been simulated based on SPICE at a transistor level of 0.18um. A reference signal of 20kHz is used for the generation of a clock at 140MHz. Frequency divider circuits utilize BD QFG Pass transistor logic PLLs as principles. To achieve an almost 10GHz frequency, the frequency divider is utilized.