Self-Adapting Power Density Sampling for On-Chip Thermal Prediction With Transistor-Level Granularity

With the rapid increase in chip scale, today’s high-performance integrated circuits are facing increasingly complex thermal management challenges. It is often time-consuming to obtain a sufficiently fine-grained temperature distribution during full-chip thermal analysis. In this article, we propose a novel and efficient on-chip thermal prediction method based on a self-adapting power density sampling technique. The new method consists of a few steps. First, a partitioning strategy is employed based on the power density sampling technique on the layout, where each sample point corresponds to a distinct subregion. Analyzing the power information of standard cells within each subregion, we generate a tile-based power density map (PDM). Subsequently, the Sobel convolution, threshold filtering, K-means clustering, and self-adapting power density sampling algorithms are applied to the PDM to identify critical subareas (CSAs) within the layout and ensure the precision of temperature predictions in these areas. Finally, by conducting parallel finite element method (FEM) based thermal simulations on subregions, we efficiently extract critical temperature information (critical T info.) for the chip. This encompasses identifying the subregions with the highest average temperature (Tavg), pinpointing the coordinates of peak temperature (Tpeak) occurrences, and highlighting areas with notable temperature gradients (Tgrad). Our approach not only achieves precise temperature results with an error margin of about 4% but also outperforms traditional FEM full-chip simulations in computational efficiency while providing a fine-grained thermal map of the chip.