An Energy-Efficient Multiplier Using Hybrid Approximate Logic Synthesis for Mixed-Quantization CNNs

Approximate computing is an emerging paradigm that, by relaxing the requirement for full accuracy in convo-lutional neural networks (CNNs), offers benefits in the design area and power consumption. In circuit design, approximate logic synthesis (ALS) is to discover and synthesize the approx-imate circuits automatically, given an exact circuit description. This paper proposes a Hybrid ALS Flow which composes Re-partition XOR-BMF ALS and Cartesian Genetic Programming ALS (CGP-based ALS), and designs the Hessian-aware Mixed-quantization CNNs. This paper designs an 8-bit approximate multiplier using the proposed Hybrid ALS Flow and applies it to the Mixed-quantization CNNs. Experiments show that the proposed Re-partition XOR-BMF ALS has better design space exploration than the BLASYS. Compared to the exact Multiplier, the designed approximate multiplier reduces the power delay product (PDP) by 56.17% under an industry 28nm process technology with the power supply of O.8V, while the accuracy loss is only 1.33% and 2.36% in VGG16 and Resnet50 on CIFARI00.