Design of Low Power and High Speed 1-bit Full Adder for DSP Applications

This paper deals with the design of the full adder circuit using the Cadence virtuoso 180nm technology. The entire circuit of the full adder consists of generation of XOR- XNOR, sum and carry. The adder is implemented in such a way that it meets the specifications of full voltage output swing and less delay. The performance of the full adder is observed using the cadence tool. The circuit contains the characteristics of the novel circuit which is really essential in order to gain the utilization of it in real life applications.