A Novel Device Design with Enlarged Storage Region for Retention Enhancement of 1T DRAM Cell

Dynamic random-access memory (DRAM) is popular as a main memory due to fast and reliable memory. DRAM has a simple architecture with only one transistor and one capacitor, making it low-power and highly integrated [1] . However, the DRAM cell faces some issues, such as current leakage at the nanoscale device level and the need for periodic refresh. To overcome these issues, researchers are looking into utilizing a floating body of single Silicon-on-Insulator (SOI) MOSFETs as charge storage [2] – [4] . The Capacitorless DRAM (1T DRAM) cell operations are based on charge (hole) generation and recombination [2] – [4] . Accumulation of holes in the floating body represents the state “1”, while evacuation of holes from the body is the state “0”. The difference between these states is termed the sensing margin ( SM ), and retention time ( T ret ) is evaluated at a time when the difference between these states reaches 50% of its maximum value [2] – [4] . In this work, we have proposed a new device design with an elongated storage region to improve the retention time of 1T DRAM cell at a shorter gate length and higher temperature.