Fault-Tolerant Reversible-Logic Based RO-PUF for Secure Device Authentication

Protecting data and hardware is vital, driving the adoption of Physically Unclonable Functions (PUFs) for generating unique circuit signatures. This paper introduces a fault-tolerant system featuring a ring-oscillator (RO) based PUF, utilizing a reversible logic (RL) design. The proposed system comprises various sub-systems such as Fault-Tolerant RL-based inverter design, Reversible-Logic designing, Fault-Detection module, Fault-free path selection module, and the Reversible RO-PUF module. The proposed design is implemented on a Basys-3 FPGA board for calculating various PUF parameters. It is observed that the uniqueness, uniformity, and bit-aliasing of the proposed design at 27°C are 49.40%, 51.20%, and 48.30%, respectively. Further, bit-error-rate (BER), reliability, and key error rate (KER) are determined at three different temperatures, and the best results obtained are 0.003%, 99.7%, and 0.092 at 40°C, respectively. Compared to conventional PUFs, the proposed design showcases higher reliability (0.002% to 0.11%) and significantly reduced BER and KER (
$1.67\times $
to
$22.67\times $
, and
$1.6\times $
to
$8.02\times $
respectively). The proposed design also passed 15 NIST tests against conventional RO-PUF, which could pass only 11 NIST tests. We have also tested the resilience of different PUF designs against three machine-learning models with the best accuracy of 58.9% against the Logistic Regression model.