A 2.5-A 3-ns-Response-Time Calibration-Free Hybrid LDO Using Scalable Self-Clocked Stochastic Flash-ADC for In-Loop Quantization

This paper presents a dual-loop hybrid low-dropout regulator (LDO) to resolve the conflicts between transient response and load capability. At the digital end, a scalable stochastic flash analog-to-digital converter (SF-ADC) performs fast loop control based on Gaussian-distributed input offset voltage (
$V_{\text {OS}}$
), enhancing load transient response while reducing circuit complexity. In the analog loop, a fully differential error amplifier (EA) is implemented to suppress the nonlinearity of the SF-ADC, resulting in a fine-regulated output with a 1.67mV/A load regulation. Moreover, the SF-ADC and the power gates (PGs) are implemented with digital standard cells only, being free of external clocks and extra calibrations. Fabricated in a 65-nm CMOS process, the proposed LDO achieves 2.5-A maximum load current (
$I_{\text {L,MAX}}$
) within an active area of 0.127 mm2. Under a 1.3A/0.8ns current up-stepping, the LDO achieves a 3-ns response time, and the measured output droop (
$V_{\text {DRP}}$
) is 127 mV.